1. Field of the Invention
The present invention relates to a semiconductor device having a silicon layer in a gate electrode and, more particularly, to a semiconductor device having a gate electrode including a silicon layer doped with boron and phosphorous. The present invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
Gate electrodes of a semiconductor device generally include a silicon layer as an undermost conductive layer formed on a gate insulating film. FIG. 1 shows the structure of a gate electrode formed on a silicon substrate in a typical semiconductor device. The semiconductor device, generally designated by numeral 40, includes gate electrodes having a dual polymetal structure. The dual polymetal structure is such that a silicon layer in the gate electrodes of pMOSFETs is doped with p-type impurities, whereas a silicon layer in the gate electrodes of nMOSFETs is doped with n-type impurities.
More specifically, the semiconductor device 40 includes a silicon substrate 11 having a surface area divided into a plurality of pMOS areas 10A and a plurality of nMOS areas 10B by an element isolation region 12 made of silicon oxide (SiO2). The pMOS areas 10A each include an n-well 13 doped with phosphorous in the surface region of the silicon substrate 11, whereas the nMOS areas 10B each include a p-well 14 doped with boron in the surface region of the silicon substrate 11. A gate insulating film 15 is made of silicon oxynitride formed on the surface of the silicon substrate 11. The silicon oxynitride has a function of preventing the boron doped in the p-type gate silicon layer from penetrating therethrough and diffusing toward the silicon substrate 11.
In the pMOS area 10A, the gate electrode 16 of pMOSFET including a 120-nm-thick p-type polysilicon layer 18a, a tungsten nitride (WN) layer 19, and a tungsten layer 20 is formed on the gate insulating film 15. The p-type polysilicon layer 18a is doped with boron at a dosage of 3×1015 cm−2.
In the nMOS area 10B, the gate electrode 17 of nMOSFET including a 120-nm-thick n-type silicon layer 18b, a tungsten nitride layer 19 and a tungsten layer 20 is formed on the gate insulting film 15. The n-type polysilicon layer 18b is doped with phosphorous at a dosage of 4×10015 cm−2.
A silicon nitride film (Si3N4) 21 is formed on the gate electrodes 16, 17, and a silicon nitride sidewall 22 is formed on the wall of the gate electrodes 16, 17 and silicon nitride film 21. Lightly-doped p-type source/drain regions 23 are formed in the surface region of the n-well 13 on both sides of the gate electrode 16, and heavily-doped p-type source/drain regions 25 encircle the lightly-doped p-type source/drain regions 23. Lightly-doped n-type source/drain regions 24 are formed in the surface region of the p-well 14 on both sides of the gate electrode 17, and heavily-doped n-type source/drain regions 26 encircle the lightly-doped p-type source/drain regions 24.
FIGS. 2A to 2D show consecutive steps of a fabrication process for forming a semiconductor device such as shown in FIG. 1. An element isolation region 12 made of a silicon oxide film is formed on a portion of the surface of the silicon substrate 11 for isolation of the pMOS areas and nMOS areas, as shown in FIG. 2A. Subsequently, phosphorous and boron are selectively implanted into the pMOS areas 10A and nMOS areas 10B, respectively, followed by a heat treatment for thermally diffusing implanted phosphorous and boron. This heat treatment activates those dopants to form n-wells 13 and p-wells 14 in the pMOS areas 10A and nMOS areas 10B, respectively. A thin silicon oxynitride film 15a is then deposited to cover the element isolation region 12 and the silicon substrate 11, followed by depositing a 120-nm-thick amorphous silicon layer 31 by using a CVD technique.
Thereafter, as shown in FIG. 2A, boron is implanted into the surface region of the amorphous silicon layer 31 at a dosage of 3×1015 cm−2, followed by forming a photoresist pattern 32 to cover the pMOS areas 10A and expose the nMOS areas 10B by using a photolithographic technique. Subsequently, as shown in FIG. 2B, phosphorous is implanted into the exposed surface portion of the amorphous silicon layer 31 in the nMOS areas 10B at a dosage of 4×1015 cm−2. The dosages of the phosphorous and boron are set so that the difference between the dosages per unit thickness of the film is equal to or above 1×1020 cm−3.
The boron thus implanted allows the portion of the amorphous silicon layer 31 in the pMOS areas 10A to assume a p-type layer. However, the other portion of the amorphous layer 31 in the nMOS areas 10B assumes an n-type layer because the phosphorous is implanted at the dosage higher than the dosage of the boron. This technique simplifies the process for obtaining the p-type and n-type amorphous silicon layers 31 by using a single photolithographic step.
Thereafter, an annealing treatment is performed at a substrate temperature of 950° C. for 20 seconds. This annealing allows the implanted phosphorous and boron to diffuse toward the silicon oxynitride film 15a and also activates those dopants. The annealing also poly-crystallizes the amorphous silicon layer 31, thereby forming a p-type polysilicon layer 18a in the pMOS areas 10A and an n-type polysilicon layer 18b in the nMOS areas 10B. After removing the photoresist pattern 32, a tungsten nitride layer 19 is deposited using a CVD technique. Subsequently, a tungsten layer 20 is deposited by a sputtering technique, followed by forming a silicon nitride film 21 thereon using a CVD technique.
The silicon nitride film 21 is patterned using a photolithographic and etching technique, and used as a hard mask in a dry etching step for patterning the tungsten layer 20, tungsten nitride layer 19, p-type polysilicon layer 18a and n-type polysilicon layer 18b. Thus, the pMOS gate electrodes 16 including the p-type polysilicon layer 18a, tungsten nitride layer 19 and tungsten layer 20, which are consecutively deposited on the silicon oxynitride film 15a, are formed in the pMOS areas 10A. Similarly, the nMOS gate electrodes 17 including the n-type polysilicon layer 18b, tungsten nitride layer 19 and tungsten layer 20, which are consecutively deposited on the silicon oxynitride film 15a, are formed in the nMOS areas 10B. The structure after this step is shown in FIG. 2D.
Thereafter, boron is selectively implanted through the silicon oxynitride film 15a into the surface region of the n-wells 13 in the pMOS areas 10A by using the silicon nitride film 21 in the pMOS areas 10A as a mask. This step provides lightly-doped p-type source/drain regions 23 in the surface region of the n-well 13 on both sides of the gate electrodes 16. Subsequently, phosphorous is selectively implanted through the silicon oxynitride film 15a into the surface region of the p-wells 14 in the nMOS areas 10B by using the silicon nitride film 21 in the nMOS areas 10B as a mask. This step provides lightly-doped n-type source/drain regions 24 in the surface region of the p-well 14 on both sides of the gate electrodes 17.
Thereafter, a silicon nitride film is deposited using a CVD technique, and etched-back to form silicon nitride sidewall films 22 on the side surfaces of the silicon nitride films 21 and the gate electrodes 16, 17. Subsequently, exposed silicon oxynitride film 15a is removed to leave the gate insulating film 15.
Thereafter, boron is selectively implanted in the surface region of the n-wells 13 in the pMOS areas 10A by using the silicon nitride film 21 and sidewall films 22 as a mask. This step provides heavily-doped p-type source/drain regions 25 encircling the lightly-doped p-type source/drain regions 23. Subsequently, phosphorous is selectively implanted in the surface region of the p-wells 14 in the nMOS areas 10B by using the silicon nitride film 21 and sidewall films 22 as a mask. This step provides heavily-doped n-type source/drain regions 26 encircling the lightly-doped n-type source/drain regions 24. Thus, the structure shown in FIG. 1 is obtained. Thereafter, contact plugs, via plugs and interconnects are formed using known processes to complete a DRAM device 40.
The dual-polymetal structure as described above is described in Patent Publication JP-A-2003-31683, for example.